Semiconductor memory devices are generally divided into volatile semiconductor memory devices that lose data as time passes, such as a dynamic random access memory (DRAM) device or a static random access memory-(SRAM) device, and non-volatile semiconductor memory devices. The non-volatile semiconductor memory devices have characteristics that maintain data stored therein even though time passes by. Thus, non-volatile semiconductor memory devices, such as flash memory devices, of which data may be electrically input and output, are widely used.
In a conventional flash memory device, a memory cell storing data generally has a stacked structure that includes a tunnel oxide layer formed on a silicon substrate, a floating gate formed on the tunnel oxide layer, a dielectric layer formed on the floating gate and a control gate formed on the dielectric layer. In the memory cell of a flash memory device having the above structure, data may be stored by injecting electrons into the floating gate while applying proper voltages to the control gate and the substrate. Here, the dielectric layer may maintain electrons accumulated in the floating gate and transfer the voltage applied to the control gate into the floating gate.
FIG. 1 is a cross-sectional view illustrating a conventional non-volatile semiconductor memory device.
Referring to FIG. 1, the conventional non-volatile semiconductor memory device includes a tunnel oxide layer 10 formed on a semiconductor substrate 5 having an isolation layer (not shown), a floating gate 15 formed on the tunnel oxide layer 10, a dielectric layer 35 formed on the floating gate 15, and a control gate 40 formed on the dielectric layer 35. The dielectric layer 35 has an oxide/nitride/oxide (ONO) structure in which a first oxide film 20, a nitride film 25 and a second oxide film 30 are formed. The floating gate 15 and the control gate 40 generally include polysilicon doped with impurities.
In conventional non-volatile semiconductor memory devices, data may be stored or erased by injecting or extracting electrons into or out of the floating gate 15 while applying predetermined voltages to the control gate 40 and the semiconductor substrate 5. Here, the dielectric layer 35 maintains the electrons charged in the floating gate 15 and transfers the predetermined voltage to the floating gate 15. However, in conventional non-volatile semiconductor memory devices having the above construction, since the dielectric layer 35 has several films of oxide and the nitride, the dielectric layer may not have a sufficient dielectric constant, and also, a process for forming the dielectric layer may be complicated. Additionally, the dielectric layer may be somewhat thick because the dielectric layer includes several films.
To solve the above-mentioned problems, Korean Laid-Open Patent Publication No. 1998-32692 discloses a semiconductor device including a dielectric layer formed using aluminum oxide (Al2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5) or vanadium oxide (V2O5) doped with an element in Group IV, such as zirconium (Zr), silicon (Si), titanium (Ti) or hafnium (Hf). In addition, Korean Laid-Open Patent Publication No. 1999-77767 discloses a floating gate memory device having a dielectric layer that includes aluminum oxide, yttrium oxide, aluminum oxide doped with an element in Group IV, such as zirconium or silicon (Si), yttrium oxide doped with an element in Group IV, or tantalum oxide doped with an element in Group IV. However, when the dielectric layer including the metal oxide doped with the element in Group IV is employed in a non-volatile semiconductor memory device, even though the dielectric layer may have a reduced thickness, a leakage current may be generated from the dielectric layer, and also, the dielectric layer may not have a sufficient dielectric constant.